HDSP2000

hdsp2000-00

 

hdsp2000-01

hdsp2000-02

hdsp2000-03

hdsp2000-04
datasheet hdsp200x

HDSP-2000 :  STANDARD RED
HDSP-2001 :  YELLOW
HDSP-2002 :  HIGH EFFICIENCY RED
HDSP-2003 :  HIGH PERFORMANCE GREEN

Description
The HDSP-2000/-2001/-2002/-2003 series of displays are 3.8 mm 0.15 inch 5 x 7 LED arrays for display of alphanumeric information. These devices are available in standard red, yellow, high efficiency red, and high performance green. Each four character cluster is contained in a 12 pin dual-inline package. An on-board SIPO Serial-In-Parallel-Out 7-bit shift register associated with each digit controls constant current LED row drivers. Full character display is achieved by external column strobing.

Electrical Description
The HDSP·200X series of four character alphanumeric displays have been designed to allow the user maximum flexibility in interface electronics design. Each four character display module features DATA IN and DATA OUT terminals arrayed for easy PC board interconnection. DATA OUT represents the output of the 7th bit of digit number 4 shift register. Shift register clocking occurs on the high to low transition of the clock input. The like Columns of each character in a display cluster are tied to a single pin. Figure 5 is the block diagram for the displays. High true data in the shift register enables the output current mirror driver stage associated with each row of LED’s in the 5 x 7 diode array. The TTL compatible VB input may either be tied to Vcc for maximum display intensity or pulse width modulated to achieve intensity control and reduction in power consumption. In the normal mode of operation. input data for digit 4 column 1 is loaded into the 7 on-board shift register locations 1 through 7. Column 1 data for digits 3, 2 and 1 is similarly shifted Into the display shift register locations. The column 1 input is now enabled for an appropriate period of time T. A similar process is repeated for columns 2. 3. 4 and 5. If the time necessary to decode and load data Into the shift register is t, then with 5 columns, each column of the display is operating at a duty factor of: D.F. = T / 5(t+T)
The time frame, t + T, allotted to each column of the display is generality chosen to provide the maximum duty factor consistent with the minimum refresh rate necessary to achieve a flicker free display. For most strobed display systems, each column of the display should be refreshed turned on at a minimum rate of 100 times per second. With columns to be addressed. this refresh rate then gives a value for the time t + T of: 1/ (5 * 100) = 2 msec If the device is operated at 3.0 MHz clock rate maximum. it is possible 10 maintain t << T. For short display strings, the duty factor will then approach 20%. For further applications information. refer to HP Application Note 1016.

 

 

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